1. Field of the Invention
The present invention relates to a method for soft-programming an electrically erasable nonvolatile memory device and to an electrically erasable nonvolatile memory device implementing the soft-programming method.
2. Description of the Related Art
As is known, nonvolatile memories comprise a memory array formed by memory cells arranged in rows and columns, in which wordlines connect gate terminals of memory cells arranged on the same row and bitlines connect drain terminals of memory cells arranged on the same column.
It is likewise known that in a nonvolatile floating-gate memory cell the storage of a logic state is carried out by programming the threshold voltage of the memory cell through the definition of the quantity of electrical charge stored in the floating-gate region.
According to the information stored, the memory cells are distinguished into erased memory cells (logic state stored “1”), in which no electrical charge is stored in the floating-gate region, and in written or programmed memory cells (logic state stored “0”) in which there is stored in the floating-gate region an electrical charge sufficient to determine a sensible increase in the threshold voltage of the memory cells.
In nonvolatile memories, moreover, the memory array is generally divided into sectors, each one of which is formed by a set of memory cells on which it is possible to carry out simultaneously the same operation, generally an erasure operation. In particular, in nonvolatile memories organized into sectors it is possible to carry out reading and programming of individual memory cells of a sector and simultaneous erasure of all the memory cells of the sector, and the latter operation is rendered possible by the fact that the memory cells belonging to the same sector have source terminals connected to one another.
Erasure of a nonvolatile memory carried out sector by sector is a cumulative operation, i.e., it acts simultaneously and indistinctly on all the memory cells of the sector, and is very complex in so far as it requires not just some preparatory steps to be carried out prior to executing the erasure proper, during which the electrical charges in the floating-gate region are extracted and consequently the threshold voltage of the memory cells themselves is reduced, but also requires verifications and possible modifications subsequent to the erasure proper in the case where the result of the erasure is not fully satisfactory.
In particular, to erase a sector there is first of all performed an operation of pre-conditioning, also known as “program-all-0”, i.e., an operation whereby all the memory cells of the sector are taken to the programmed state irrespective of their current state. This is due to the fact that, if there were to be erased a sector in which some of the memory cells are written but others are already erased, during the erasure there would occur an over-erasure of the memory cells already erased, which, with a fair degree of likelihood, would become depleted memory cells, i.e., memory cells that have negative threshold voltage and thus drain a current even when their gate terminal is set at ground voltage. These depleted memory cells are particularly troublesome in so far as they simulate the constant presence of erased memory cells in the respective columns to which they belong and thus cause all the memory cells belonging to said columns to be read as erased irrespective of their actual state.
In order to prevent this phenomenon and to render the history of all the memory cells belonging to the same sector uniform, there is hence performed the step of writing the entire sector, and then, following upon the operation of pre-conditioning, all the memory cells of the sector are programmed.
Next, there is carried out the erasure step proper, during which the electrical charges in the floating-gate region are extracted, and consequently the threshold voltage of the memory cells is reduced.
In order to carry this out, between the source terminal and the gate terminal of each memory cell there is applied a high electric field such as to enable the electrons to abandon the floating-gate region thanks to the so-called Fowler-Nordheim tunnelling effect.
The application of the electrical potential necessary to extract the electrical charges from the floating-gate region can occur in different ways. One of the methodologies that can, for example, be used to extract the electrical charges from the floating-gate region is known in the literature as “negative gate erasure” and basically envisages leaving floating the drain terminal of the memory cell to be erased and applying to the gate terminal a negative voltage pulse having typically an amplitude of 10 V and a time duration of the order of 10 ms, and to the source and body terminals a succession of voltage pulses the amplitude of which is variable in staircase fashion from a minimum value of 3 V to a maximum value of 8 V, with steps of 300 mV.
At the end of the erasure pulse, there is then carried out an operation of verification on all the memory cells of the sector in order to check the value of their threshold voltages, and this verification is made by performing a marginated reading that will guarantee correct recognition of the memory cell in the normal reading mode.
In particular, the verification operation scans all the memory cells of the sector and is interrupted when a memory cell that does not pass the test is found. At this point the next erasure pulse is applied. Hence, the erasure process consists in the application of an erasure pulse, followed by a subsequent step of verification until all the memory cells have a threshold voltage lower than a reference threshold voltage, which is the threshold voltage of the reference memory cell used during the verification operation. Once the voltage pulses applied to the source and body terminals have reached their maximum amplitude, if the memory cells of the sector are not yet all erased, then there is envisaged a second step of pure electrical erasure, during which further erasure pulses are applied both to the gate terminals and to the source and body terminals of the memory cells of the sector, up to a given maximum number, in which the amplitude of the pulses applied to the source and body terminals of the memory cells is equal to the maximum amplitude envisaged.
At the end of pure electrical erasure, all the memory cells of the sector have threshold voltages presenting a basically gaussian distribution, on which there is superimposed a possible “tail” due to the depleted memory cells.
The sector erasure step cannot, however, yet be deemed concluded because it is still necessary to ensure that there will not be depleted memory cells that can induce errors during the reading step. As previously mentioned, in fact, since these memory cells have a negative threshold voltage and thus drain a current even when their gate terminals are set at ground voltage, they can vitiate the subsequent operation of reading of the memory device in so far as they simulate the constant presence of erased memory cells in the respective columns to which they belong and thus cause all the memory cells belonging to these columns to be read as erased irrespective of their actual state.
Hence, the erasure step proper is followed by a step of search and re-programming of the depleted memory cells, known also as “soft-programming”, in which there is verified the presence of a leakage current in the columns of the memory array by biasing all the rows of the array at ground voltage.
When a column presenting this anomaly is identified, then the first memory cell of the column is addressed, and a programming pulse having a pre-set amplitude is applied to its gate terminal in order to shift slightly the threshold voltage of the memory cell towards higher values.
This is followed by reading of the second memory cell of the same column: if no leakage current is present in the memory cell, then this means that the depleted memory cell was the preceding one that has already been recovered; otherwise, the memory cell considered is programmed, and so on up to the end of the column.
Once the end of the column has been reached, the verification operation is then repeated, and in the case where a leakage current is still present, the procedure described above is repeated, increasing, however, the amplitude of the programming pulse applied to the gate terminals of the memory cells during programming.
In practice, soft-programming is never carried out on a single memory cell at a time, but rather on a given number of memory cells at a time that is linked to the number of programming circuits (program loads) with which the memory device is provided, currently sixteen. In particular, soft-programming is carried out by addressing a number of memory cells equal to the number of program loads and by soft-programming only those memory cells addressed that effectively require this operation. The number of memory cells that are simultaneously soft-programmed is generally known, in the technical field, as “soft-programming parallelism” or “soft-programming multiplicity”.
To compete in the sectors of emerging markets of portable electronic apparatuses, such as, for example, MP3 players and digital cameras, nonvolatile memory devices are currently subject to a revision of their traditional specifications; in particular they are the subject of in-depth studies aimed, among other things, at reducing erasure time.
A contribution to reduction in erasure time could come from the reduction of soft-programming time, which, at least in principle, could be obtained by increasing the parallelism with which this operation is performed.
For example, reduction in soft-programming time could be obtained simply by doubling the number of program loads, but this would entail, in the case where all the memory cells addressed were to require soft-programming, a doubling of the current absorbed in the soft-programming step.
In order to generate this current, it is possible to act in two ways: either to generate the current necessary outside of the memory device, using an appropriate current generator, and supply it to a purposely provided pin of the memory device, or else to double the size of the charge pump, which, in the memory device, is dedicated to the generation of high currents.
The first solution runs, however, counter to the trend of current markets of semiconductor memory devices, which, instead, requires reduction of both the number of voltage supplies in the memory device and their absolute voltage value, whilst the second solution would lead to a significant increase in the area occupied by the charge pump on the silicon and thus to an increase in the cost of the memory device.